Ordering InformationSee Table 2 on page 5MIMX8QMxAVUxxAxNXP SemiconductorsData Sheet: Technical DataDocument Number: IMX8QMAECRev. 0, 10/2019Package Information29 x 29 mm package case outline© 2018-2019 NXP B.V.NXP reserves the right to change the detail specifications as may be required to permit improvements in the design ofits products.1IntroductionThe i.MX 8 Family consists of three processors:i.MX 8QuadMax, 8QuadPlus, and 8DualMax. This datasheet covers the i.MX 8QuadMax processor, which iscomposed of eight cores (two Arm® Cortex®-A72, fourArm Cortex®-A53, and two Arm Cortex®-M4F), dual32-bit GPU subsystems, 4K H.265 capable VPU, anddual failover-ready display controllers. This processorsupports a single 4K display (with multiple displayoutput options, including MIPI-DSI, HDMI, eDP/DP,and LVDS), or multiple smaller displays. Memoryinterfaces supporting LPDDR4, Quad SPI/Octal SPI(FlexSPI), eMMC 5.1, RAW NAND, SD 3.0, and a widerange of peripheral I/Os such as PCIe 3.0, provide wideflexibility. Advanced multicore audio processing issupported by the Arm cores and a high performanceTensilica® HiFi 4 DSP for pre- and post-audioprocessing as well as voice recognition.i.MX 8QuadMaxAutomotive andInfotainmentApplications Processors1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 51.2System Controller Firmware (SCFW) Requirements51.3Related resources . . . . . . . . . . . . . . . . . . . . . . . . . . 52Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.1Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.1Special Signal Considerations. . . . . . . . . . . . . . . . 143.2Recommended Connections for Unused Interfaces144Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 154.1Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . . 154.2Power supplies requirements and restrictions. . . . 274.3PLL electrical characteristics. . . . . . . . . . . . . . . . . 304.4On-chip oscillators. . . . . . . . . . . . . . . . . . . . . . . . . 354.5I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 374.6I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 444.7Output Buffer Impedance Parameters. . . . . . . . . . 464.8System Modules Timing . . . . . . . . . . . . . . . . . . . . 514.9General-Purpose Media Interface (GPMI) Timing . 544.10 External Peripheral Interface Parameters . . . . . . . 634.11 Analog-to-digital converter (ADC) . . . . . . . . . . . . 1215Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 1245.1Boot mode configuration pins . . . . . . . . . . . . . . . 1245.2Boot devices interfaces allocation . . . . . . . . . . . . 1256Package information and contact assignments . . . . . . 1276.1FCPBGA, 29 x 29 mm, 0.75 mm pitch . . . . . . . . 1277Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
