NXP SemiconductorsData Sheet: Technical DataDocument Number: IMX6SDLAECRev. 9, 11/2018Package InformationPlastic PackageBGA Case 2240 21 x 21 mm, 0.8 mm pitchOrdering InformationSee Table 1 on page 3NXP Reserves the right to change the production detail specifications as may berequired to permit improvements in the design of its productsMCIMX6UxAxxxxxBMCIMX6UxAxxxxxCMCIMX6UxAxxxxxDMCIMX6SxAxxxxxBMCIMX6SxAxxxxxCMCIMX6SxAxxxxxD1IntroductionThe i.MX 6Solo/6DualLite automotive and infotainmentprocessors represent the latest achievement in integratedmultimedia-focused products offering high-performanceprocessing with a high degree of functional integration.These processors are designed considering the needs ofthe growing automotive infotainment, telematics, HMI,and display-based cluster markets.The processors feature advanced implementation ofsingle/dual Arm® Cortex®-A9 core, which operates atspeeds of up to 1 GHz. They include 2D and 3D graphicsprocessors, 1080p video processing, and integratedpower management. Each processor provides a 32/64-bitDDR3/DDR3L/LPDDR2-800 memory interface and anumber of other interfaces for connecting peripherals,such as WLAN, Bluetooth®, GPS, hard drive, displays,and camera sensors.i.MX 6Solo/6DualLiteAutomotive andInfotainmentApplications Processors1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.1Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .31.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51.3Updated Signal Naming Convention . . . . . . . . . . . .92Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .102.1Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .103Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113.1Special Signal Considerations . . . . . . . . . . . . . . . .213.2Recommended Connections for Unused AnalogInterfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .234.1Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . .234.2Power Supplies Requirements and Restrictions . .334.3Integrated LDO Voltage Regulator Parameters . . .344.4PLL’s Electrical Characteristics . . . . . . . . . . . . . . .364.5On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . .384.6I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .394.7I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .444.8Output Buffer Impedance Parameters . . . . . . . . . .494.9System Modules Timing . . . . . . . . . . . . . . . . . . . . .524.10 General-Purpose Media Interface (GPMI) Timing .644.11 External Peripheral Interface Parameters . . . . . . .725Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . .1345.1Boot Mode Configuration Pins . . . . . . . . . . . . . . .1345.2Boot Device Interface Allocation . . . . . . . . . . . . .1356Package Information and Contact Assignments . . . . . .1366.1Updated Signal Naming Convention . . . . . . . . . .1366.221x21 mm Package Information. . . . . . . . . . . . . .1377Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
