®IncludesMAX 7000AEAltera Corporation1MAX 7000AProgrammable LogicDeviceSeptember 2003, ver. 4.5Data SheetDS-M7000A-4.5Features...■High-performance 3.3-V EEPROM-based programmable logicdevices (PLDs) built on second-generation Multiple Array MatriX(MAX®) architecture (see Table 1)■3.3-V in-system programmability (ISP) through the built-inIEEE Std. 1149.1 Joint Test Action Group (JTAG) interface withadvanced pin-locking capability–MAX 7000AE device in-system programmability (ISP) circuitrycompliant with IEEE Std. 1532–EPM7128A and EPM7256A device ISP circuitry compatible withIEEE Std. 1532■Built-in boundary-scan test (BST) circuitry compliant withIEEE Std. 1149.1■Supports JEDEC Jam Standard Test and Programming Language(STAPL) JESD-71■Enhanced ISP features–Enhanced ISP algorithm for faster programming (excludingEPM7128A and EPM7256A devices)–ISP_Done bit to ensure complete programming (excludingEPM7128A and EPM7256A devices)–Pull-up resistor on I/O pins during in-system programming■Pin-compatible with the popular 5.0-V MAX 7000S devices■High-density PLDs ranging from 600 to 10,000 usable gates■Extended temperature rangef For information on in-system programmable 5.0-V MAX 7000 or 2.5-VMAX 7000B devices, see the MAX 7000 Programmable Logic Device FamilyData Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.
