®Altera Corporation1CycloneFPGA FamilyMarch 2003, ver. 1.1Data SheetDS-CYCLONE-1.1IntroductionPreliminaryInformationThe CycloneTM field programmable gate array family is based on a 1.5-V,0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logicelements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memoryrequirements, Cyclone devices are a cost-effective solution for data-pathapplications. Cyclone devices support various I/O standards, includingLVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,32-bit peripheral component interconnect (PCI), for interfacing with andsupporting ASSP and ASIC devices. Altera also offers new low-cost serialconfiguration devices to configure Cyclone devices.Features...■2,910 to 20,060 LEs, see Table 1■Up to 294,912 RAM bits (36,864 bytes)■Supports configuration through low-cost serial configuration device■Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards■Support for 66-MHz, 32-bit PCI standard■Low speed (311 Mbps) LVDS I/O support■Up to two PLLs per device provide clock multiplication and phaseshifting■Up to eight global clock lines with six clock resources available perlogic array block (LAB) row■Support for external memory, including DDR SDRAM (133 MHz),FCRAM, and single data rate (SDR) SDRAM■Support for multiple intellectual property (IP) cores, includingAltera MegaCore functions and Altera Megafunctions PartnersProgram (AMPPSM) megafunctionsNote to Table 1:(1)This parameter includes global clock pins.Table 1. Cyclone Device FeaturesFeatureEP1C3EP1C4EP1C6EP1C12EP1C20LEs2,9104,0005,98012,06020,060M4K RAM blocks (128× 36 bits)1317205264Total RAM bits59,90478,33692,160239,616294,912PLLs12222Maximum user I/O pins (1)104301185249301
