74AUP1T17Low-power buffer with voltage-level translatorRev. 3 — 25 January 2022Product data sheet1. General descriptionThe 74AUP1T17 provides the single buffer function. This device ensures a very low static anddynamic power consumption across the entire VCC range from 2.3 V to 3.6 V.The 74AUP1T17 is designed for logic-level translation applications with input switching levels thataccept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supplyvoltage.The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to2.3 V.This device is fully specified for partial power-down applications using IOFF. The IOFF circuitrydisables the output, preventing the damaging backflow current through the device when it ispowered down.Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entireVCC range.2. Features and benefits• Wide supply voltage range from 2.3 V to 3.6 V• High noise immunity• ESD protection:• HBM JESD22-A114F Class 3A exceeds 5000 V• CDM JESD22-C101E exceeds 1000 V• Low static power consumption; ICC = 1.5 μA (maximum)• Latch-up performance exceeds 100 mA per JESD 78 Class II• Inputs accept voltages up to 3.6 V• Low noise overshoot and undershoot < 10 % of VCC• IOFF circuitry provides partial power-down mode operation• Specified from -40 °C to 85 °C and -40 °C to 125 °C3. Ordering informationTable 1. Ordering informationPackageType numberTemperature range NameDescriptionVersion74AUP1T17GW -40 °C to 125 °CTSSOP5plastic thin shrink small outline package; 5 leads;body width 1.25 mmSOT353-174AUP1T17GX-40 °C to 125 °CX2SON5plastic thermal enhanced extremely thinsmall outline package; no leads; 5 terminals;body 0.8 × 0.8 × 0.32 mmSOT1226-3
