1.General descriptionThe LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applicationsrequiring a high level of integration and low power dissipation.The Cortex-M3 is a next generation core that offers better performance than the ARM7 atthe same clock rate and other system enhancements such as modernized debug featuresand a higher level of support block integration. The Cortex-M3 CPU incorporates a3-stage pipeline and has a Harvard architecture with separate local instruction and databuses, as well as a third bus with slightly lower performance for peripherals. TheCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranches.The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimalperformance when executing code from flash. The LPC178x/7x operates at up to120 MHz CPU frequency.The peripheral complement of the LPC178x/7x includes up to 512 kB of flash programmemory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory,External Memory Controller (EMC), LCD (LPC178x only), Ethernet, USBDevice/Host/OTG, a General Purpose DMA controller, five UARTs, three SSP controllers,three I2C-bus interfaces, one eight-channel, 12-bit ADC, a 10-bit DAC, a QuadratureEncoder Interface, four general purpose timers, two general purpose PWMs with sixoutputs each and one motor control PWM, an ultra-low power RTC with separate batterysupply and event recorder, a windowed watchdog timer, a CRC calculation engine, up to165 general purpose I/O pins, and more. The pinout of LPC178x/7x is intended to allowpin function compatibility with the LPC24xx and LPC23xx.2.Features and benefits Functional replacement for the LPC23xx and LPC24xx family devices. System: ARM Cortex-M3 processor, running at frequencies of up to 120 MHz. A MemoryProtection Unit (MPU) supporting eight regions is included. ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). Multilayer AHB matrix interconnect provides a separate bus for each AHB master.AHB masters include the CPU,USB, Ethernet, and the General Purpose DMAcontroller. This interconnect provides communication with no arbitration delaysunless two masters attempt to access the same slave at the same time. Split APB bus allows for higher throughput with fewer stalls between the CPU andDMA. A single level of write buffering allows the CPU to continue without waiting forcompletion of APB writes if the APB was not already busy.LPC178x/7x32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMCRev. 4 — 1 May 2012Preliminary data sheet
