General PurposeCopyright © 2005 by Silicon Laboratories5.5.2005Port 0LatchPort 1LatchJTAGLogicUART8 kBFLASH256 byteRAMVDDMonitorSFR BusPort 2LatchPort 3Latch8051CoreTimer 0Timer 1Timer 212-bit100 kspsADCAMUXCP0CP1AIN0-AIN31P1.0/CP0 P1.1/CP0-P1.2/CP0P1.3/CP1 P1.4/CP1-P1.5/CP1P1.6/SYSCLKP1.7P1DrvP0.0/TXP0.1/RXP0.2//INT0P0.3//INT1P0.4/T0P0.5/T1P0.6/T2P0.7/T2EXP0DrvP3.0P3.1P3.2P3.3P3.4P3.5P3.6P3.7P3DrvP2.0/NSSP2.1/MISOP2.2/MOSIP2.3/SCKP2.4P2.5P2.6P2.7P2DrvCP0 CP0-CP1 CP1-P0MUXResetExternalOscillatorCircuitSystem ClockInternalOscillatorAnalog/DigitalPowerDebug HWP1MUXCP0CP1VDDP2MUXSPIVREF1024 byteXRAMWDTPGASYSCLKTCKTMSTDITDOVDDVDDGNDGNDRSTXTAL1XTAL2NCNCNCMONENC8051F20625 MIPS, 8 kB Flash, 12-Bit ADC, 48-Pin Mixed-Signal MCUAnalog Peripherals12-Bit ADC- No missing codes- Programmable throughput up to 100 ksps- 32 external inputs (each port I/O can be configured as an ADC input on-the-fly)- Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5- Data-dependent windowed interrupt generator- VREF from external pin or VDDTwo comparators- Programmable hysteresis- Configurable to generate interrupts or resetVDD Monitor and Brown-out DetectorOn-Chip JTAG Debug- On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuitemulation- Supports breakpoints, single stepping, watchpoints, inspect/modifymemory, and registers- Superior performance to emulation systems using ICE-chips, targetpods, and sockets- Fully compliant with IEEE 1149.1 specificationSupply Voltage: 2.7 to 3.6 V- Typical operating current: 9 mA at 25 MHz- Typical stop mode current:
